2017 IEEE International Electron Devices Meeting

Welcome to the Editor Press Center. The following press materials may be downloaded from this site for pre-conference publicity for the 2017 IEDM.
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Welcome to the Editor Press Center. Check back periodically for photo and caption updates. The following press materials may be downloaded from this site for pre-conference publicity for the IEDM:

2017 IEDM Press Releases:

2017 IEDM Photos with captions:
Selected images from the abstracts are presented in two formats:
- Word file with images associated with a highlighted paper and the caption
- JPEG file with individual high-resolution Images

Paper #2.1, "Breakthrough of Selector Technology for Cross-Point 25nm ReRAM"
S.G. Kim et al, SK Hynix
Image With Caption
2-1 Record Performance with SiO2-Based Selector, SK Hynix
High Resolution Images
2.1 Figure 1.jpg
2.1 Figure 3.jpg
2.1 Figure 14.jpg

Paper #3.7, "Towards Cube-Sized Compute Nodes: Advanced Packaging Concepts Enabling Extreme 3D Integration"
T. Brunschwiler et al, IBM/ETH/FhG/Murata/Tyndall National Institute
Image With Caption
3.7 Extreme 3D Integration.docx
High Resolution Images
3.7 Figure 1.jpg
3.7 Figure 2.jpg

Paper #4.1, "Atomistic Investigation of the Electronic Structure, Thermal Properties and Conduction Defects in Ge-rich GexSe1-x Materials for Selector Applications"
S. Clima et al, Imec/Univ. Leuven/Univ. Antwerp
Image With Caption
4-1 Atomistic Studies of Germanium-Rich Selectors.docx
High Resolution Images
4.1 Figure 4.jpg

Paper #7.6, "Thermal Effects in 3D Sequential Technology"
K. Triantopoulos et al, CEA-Leti/Univ. Grenoble Alpes/IMEP-LAHC
Image With Caption
7-6 Thermal Effects in Monolithic 3D ICs_CEA-Leti.docx
High Resolution Images
7.6 Figure 1.jpg
7.6 Figure 2.jpg
7.6 Figure 7.jpg

Paper #9.3, "“Determination of Intrinsic Phonon-Limited Mobility and Carrier Transport Property Extraction of 4H-SiC MOSFETs"
M. Noguchi et al, Mitsubishi/Univ. Tokyo
Image With Caption
9-3 New Discoveries About SiC Mobility_University of Tokyo.docx
High Resolution Images
9.3 Figure 2.jpg
9.3 Figure 2a.jpg
9.3 Figure 2b.jpg
9.3 Figure 6.jpg

Paper #10.1, "Nanofluidics for Cell and Drug Delivery"
N. Di Trani et al, Houston Methodist Research Institute/Politecnico di Torino
Image With Caption
10-1 Nanofluidic Implants for Better Health_Houston Methodist Research Institute.docx
High Resolution Images
10.1 Figure 11.jpg
10.1 Figure 13.jpg

Paper #16.3, "Back-side Illuminated GeSn Photodiode Array on Quartz Substrate Fabricated by Laser-Induced Liquid-Phase Crystallization for Monolithically-Integrated NIR Imager Chip"
H. Oka et al, Osaka Univ./Hiroshima Univ.
Image With Caption
16-3 Record Performance from GeSn Backside Imager_Osaka University.docx
High Resolution Images
16.3 Figure 3.jpg
16.3 Figure 8.jpg

Paper #16.4, "Near-infrared Sensitivity Enhancement of a Back-side Complementary Metal Oxide Semiconductor Image Sensor with a Pyramid Surface for Diffraction Structure"
I. Oshiyama et al, Sony
Image With Caption
16-4 Boosting Near-Infrared Sensitivity in CMOS Imagers_Sony.docx
High Resolution Images
16.4 Figure 8.jpg

Paper #17.1, "Record Performance Top-Down In0.53Ga0.47As Vertical Nanowire FETs and Vertical Nanosheets"
S. Ramesh et al, KU Leuven/Imec
Image With Caption
17-1 Record Performance From Vertical III-V Nanowire-Nanosheet MOSFETs_KU Leuven.docx
High Resolution Images
17.1 Figure 2a.jpg
17.1 Figure 2b.jpg
17.1 Figure 2c.jpg

Paper #18.1, "Lab On SkinTM: 3D Monolithically Integrated Zero-Energy Micro/Nanofluidics and FD SOI Ion-Sensitive FETs for Wearable Multi-Sensing Sweat Applications"
F. Bellando et al, EPFL/Xsensio
Image With Caption
18-1 Lab on Skin_EPFL.docx
High Resolution Images
18.1 Figure 1.jpg
18.1 Figure 3a.jpg
18.1 Figure 3b.jpg

Paper #19.1, "A 128Gb (MLC)/192Gb (TLC) Single-Gate Vertical Channel (SGVC) Architecture 3D NAND using only 16 Layers with Robust Read Disturb, Long-Retention and Excellent Scaling Capability"
H.-T. Lue et al, Macronix
Image With Caption
19-1 Ultra-High-Density 3D NAND Technology_Macronix.docx
High Resolution Images
19.1 Figure 2.jpg
19.1 Figure 3.jpg

Paper #29.1, "A 10nm High Performance and Low-Power CMOS Technology Featuring 3rd-Generation FinFET Transistors, Self-Aligned Quad Patterning, Contact Over Active Gate and Cobalt Local Interconnects"
C. Auth et al, Intel
Image With Caption
29-1 New 10nm CMOS Platform_Intel.docx
High Resolution Images
29.1 Figure 3.jpg
29.1 Figure 13.jpg

Paper #29.5, "A 7nm CMOS Technology Platform for Mobile and High-Performance Compute Applications"
S. Narasimha et al, Globalfoundries
Image With Caption
29-5 New 7nm CMOS Platform_Globalfoundries.docx
High Resolution Images
29.5 Figure 2.jpg
29.5 Figure 11.jpg
29.5 Figure 14.jpg
29.5 Figure 16.jpg

Paper #31.2, "Computational Study of Gate-Induced Drain Leakage in 2D-Semiconductor Field-Effect Transistors"
J. Kang et al, Univ. California-Santa Barbara/Micron Technology
Image With Caption
31-2 Reducing Gate-Driven Leakage in 2D Semiconductors_UC-Santa Barbara.docx
High Resolution Images
31.2 Figure 4.jpg

Paper #37.2, "A Comparative Study of Strain and Ge Content in Si1-xGex Channel Using Planar FETs, FinFETs, and Strained Relaxed Buffer Layer FinFETs"
C. H. Lee et al, IBM/Globalfoundries
Image With Caption
37-2 Effects of Strain vs Ge Content in SiGe Transistors_IBM and Globalfoundries.docx
High Resolution Images
37.2 Figure 1.jpeg
37.2 Figure 4a.jpeg
37.2 Figure 4b.jpeg
37.2 Figure 4c.jpeg

Paper #37.4, "Vertically Stacked Gate-All-Around Si Nanowire Transistors: Key Process Optimizations and Ring Oscillator Demonstration"
H. Mertens et al, Imec/Applied Materials
Image With Caption
37-4 First Circuit Built With Si Nanowire Transistors_Imec and Applied Materials.docx
High Resolution Images
37.4 Figure 15.jpg
37.4 Figure 17.jpg

Supporting Images

ATTENDANCE AT IEDM IS COMPLIMENTARY FOR THE PRESS.
If you plan to attend, please let us know. Also, the conference organizers are planning to have a press luncheon at the beginning of the IEDM to discuss the most interesting papers and the major technology trends evident in this year's program. We encourage journalists to attend it, and details will be provided in November.

Whether you would like to do a news story, conference preview or an in-depth exploration of a particular technology, please contact one of us for the additional information or interviews you may need.

Editor Contacts:
Gary Dagastine, co-Media Relations Director, at gdagastine@nycap.rr.com or by telephone at +1 518 785 2724
Chris Burke, co-Media Relations Director, at chris.burke@btbmarketing.com or by telephone at +1 919 872 8172

Registration/attendance questions:
Can be answered by the Conference Manager Phyllis Mahoney, at phyllism@widerkehr.com or by telephone at +1 301 527 0900.
19803 Laurel Valley Place, Montgomery Village, MD 20886 USA

ABOUT IEDM
IEEE International Electron Devices Meeting (IEDM) is the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electron-device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation. The conference scope not only encompasses devices in silicon, compound, and organic semiconductors, but also emerging material systems.