2013 IEDM International Electron Devices Meeting

2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)

2013 IEEE International
Electron Devices Meeting

Washington Hilton
1919 Connecticut Ave., NW
Washington, DC USA
December 9-12, 2013

CONTACT INFORMATION:

Chris Burke
co-Media Relations Director
+1 919 872 8172
chris.burke@btbmarketing.com

Gary Dagastine
co-Media Relations Director
+1 518 785 2724
gdagastine@nycap.rr.com

The IEEE International Electron Devices Meeting (IEDM) is the world's premier forum for the presentation of advances in microelectronic, nanoelectronic and bioelectronic devices. The IEDM presents more leading work in more areas of the field than any other technical conference, encompassing silicon and non-silicon device technology, molecular electronics, nanotechnology, optoelectronics, MEMS/NEMS (micro-/nanoelectromechanical systems), energy-related devices and bioelectronics. The 59th annual IEDM conference includes a strong overall emphasis on circuit-device interaction, advanced semiconductor manufacturing, and biomedical devices.

Welcome to the Editor Press Center. The following press materials may be downloaded from this site for pre-conference publicity for the IEDM:

2013 IEDM Press Kit

IEDM Press Releases
Lead Release
Tip Sheet
(“highlights” of IEDM Technical Program)
Advance Program 400KB

2013 IEDM Photos

Selected images from the abstracts are presented in two formats:
- Word file with images associated with a highlighted
paper and the caption
- JPEG file with individual high-resolution Images.

Image Download

2.2 "High Electron Mobility Triangular InGaAs-OI nMOSFETs with (111)B Side Surfaces Formed by MOVPE Growth on Narrow Fin Structures"
T. Irisawa et al, AIST
Image With Caption
2.2, Triangular MOSFETs with InGaAs Channels - AIST
High Resolution Images
2.2 Figure 9

3.2 "Comprehensive Study of CoFeB-MgO Magnetic Tunnel Junction Characteristics with Single- and Double-Interface Scaling Down to 1X nm"
H. Sato et al, Tohoku University
Image With Caption
3.2, Thermally Stable Magnetic Tunnel Junction Memory - Tohoku University
High Resolution Image

3.2 Figure 1

9.1 "A 16nm CMOS FinFET Technology for Mobile SoC and Computing Applications"
S-Y. Wu et al, Taiwan Semiconductor Manufacturing Co.
Image With Caption
9.1, TSMC's Integrated 16-nm FinFET Technology Platform - Taiwan Semiconductor Manufacturing Co.
High Resolution Image
9.1 Figure 2
9.1 Figure 12a
9.1 Figure 12b

9.3 "Monolithic 3D Chip Integrated with 500ns NVM, 3ps Logic Circuits and SRAM"
C-H. Shen et al, National Nano Device Laboratories
Image With Caption
9.3, Monolithic 3D Chip - National Nano Device Laboratories
High Resolution Images
9.3 Figure 2
9.3 Figure 3

14.1 "200mm Wafer-Scale Integration of Sub-20nm Sacrificial Nanofluidic Channels for Manipulating and Imaging Single DNA Molecules"
C. Wang et al, IBM
Image With Caption
14.1, Nanofluidic Channels for Lab-on-Chip - IBM
High Resolution Images
14.1 Figure 1
14.1 Figure 2
14.1 Figure 5
14.1 Figure 6
14.1 Figure 12

14.3 "A Novel Side-Gated Ultrathin-Channel Nanopore FET (SGNAFET) Sensor for Direct DNA Sequencing"
I. Yanagi et al, Hitachi
Image With Caption
14.3, Novel Nanopore Sensor for DNA Sequencing - Hitachi
High Resolution Images
14.3 Figure 1
14.3 Figure 10
14.3 Figure 11

14.5 "A Novel SiNW/CMOS Hybrid Biosensor for High Sensitivity/Low Noise"
J. Lee et al, Kookmin University
Image With Caption
14.5, Hybrid Nanowire/CMOS Biosensor - Kookmin University
High Resolution Images
14.5 Figure 4
14.5 Figure 5

20.1 "Scaled P-Channel Ge FinFET With Optimized Gate Stack and Record Performance Integrated on 300mm Si Wafers"
B. Duriez et al, Taiwan Semiconductor Manufacturing Co.
Image With Caption
20.1, 300mm wafer-scale Ge FinFET - TSMC
High Resolution Images
20.1 Figure 14

20.2 "Density Scaling with Gate-All-Around Silicon Nanowire MOSFETs for the 10nm Node and Beyond"
S. Bangsaruntip et al, IBM
Image With Caption
20.2, Record Silicon Nanowire MOSFETs - IBM
High Resolution Images
20.2 Figure 1
20.2 Figure 2
20.2 Figure 3
20.2 Figure 4

21.6 "Conductive-AFM Tomography for 3D Filament Observation in Resistive Switching Devices"
U. Celano et al, IMEC
Image With Caption
21.6, Visualizing CBRAM Filaments - IMEC
High Resolution Images
21.6 Figure 12
21.6 Figure 14
21.6 Figure 16

26.1 "High Mobility Strained-Ge pMOSFETs with 0.7-nm Ultrathin EOT using Plasma Post Oxidation HfO2/Al2O3/GeOx Gate Stacks and Strain Modulation"
R. Zhang et al, University of Tokyo
Image With Caption
26.1, Fastest Ge p-MOSFET - Univ. Tokyo
High Resolution Images
26.1 Figure 1
26.1 Figure 3
26.1 Figure 12


Attendance at IEDM is complimentary for the press. If you plan to attend, please let us know. Also, the conference organizers are planning to have a press luncheon at the beginning of the IEDM to discuss the most interesting papers and the major technology trends evident in this year's program. We encourage journalists to attend it, and details will be provided in November.

Whether you would like to do a news story, conference preview or an in-depth exploration of a particular technology, please contact one of us for the additional information or interviews you may need.

Your registration/attendance questions also can be answered by the Conference Manager Phyllis Mahoney, at phyllism@widerkehr.com or by telephone at +1 301 527 0900.